1. Understanding the Original Design

prior to starting this project, i had exactly 0 knowledge on how VFDs actually worked. but after some research i think i picked up enough to understand what was happening. this video in particular was very useful in my quest to understand how VFDs work. i won’t go into much detail (the video is like, right there), but here are the basics we need to understand to make reverse engineering the design a little bit easier.

the main points to a VFD i learned are;

• there are 3 main sections to a VFD;
  • a cathode made of tungsten wire string
  • a phosphor coated anode
  • a fine grid mesh sandwiched between the anode and cathode
• VFDs typically require a voltage difference of 20-30V between the anode and cathode to illuminate the anodes
• there are two pins for the cathode (wire string) - this typically needs a voltage difference across it in some alternating waveform. the video above suggests about 3V.
• the main power draw of a VFD will occur from the cathode filament

with that in mind, let’s move on and try to understand the original design.

Attempting to reverse engineer the original PSU #

the PSU PCB is quite small and is stood off from the main display board. the below image shows the original layout.

i started off by desoldering this from the main board and found there were 6 connecting pins back to the main board. these are;

note that the -8V and CT pins are shorted, however these are not shorted on the PSU PCB - instead there is a trace on the main board which connects these two pins together.

i traced out the PCB and had drawn out to the below diagram

unfortunately this wasn’t very helpful as the transistor at reference Q3 was unlabelled across all of the displays i had in my possession. however, i knew that the ac pins were connected to the cathode pins of the VFD, so i thought i would probe the pins with my oscilloscope to see what i’d get. ultimately the probe was connected to one of the AC pins (it’s not really important which one), and the GND alligator clip to GND on the PSU.

here’s what the setup looks like;

and the below image is a screenshot from the oscilloscope.

here’s what i observed from the waveform;

• the waveform is centered around -8V (i.e. -8V DC offset)
  • this makes sense as the -8V power rail is connected to the transformer center tap
• the peak waveform values are around +4V and -3.5V (relative to DC offset)
  • relative to GND, this means the waveform peak values are -4V and -11.5V
• the frequency is around 43kHz - though this frequency does change depending on the current draw from the VFD
  • the frequency appears to be inversely proportional to the current draw from the -8V rail. i.e. as more power is drawn from the -8V rail, the waveform frequency decreases. i don’t think this is an intended design feature - rather, i believe it is an artifact caused by the simple and low cost PSU design.
• the duty cycle appears to be about 70%. not sure of the purpose of this but i may find out during the design phase.

lastly, i connected my current meter in series with the -8V rail to see the current draw. i noted about 300mA current draw when the display first receives power, and then about 280mA once the display had reached a steady state. it should be noted here that all segments illuminate when the display first receives power - this is advantageous as i get to see the theoretical maximum current draw from all of the segments.

Some other notes and thoughts #

-8V is chosen as an inverted power rail value as 12V - -8V = 20V. this is where we get the required 20V difference to drive the VFD.

the segments are controlled on the motherboard. as the fine mesh grid is voltage controlled to isolate individual segments of the VFD (much like segment displays with a common anode or cathode), the video mentioned at the top of this page talks to “activating” a segment of the VFD when the mesh voltage is “on” (i.e. positive). and “deactivating” a segment when the mesh voltage is “off” (i.e. negative). i’m assuming that the “on” and “off” voltages are 12V and 0V respectively - my guess is that the 0V potential is close enough to -8V to deflect the electrons being emitted by the cathode and therefore stop the segment illumination. consequently, if we decreased the inverted power rail to say -18V, the segments may always be illuminated.

the above was difficult to describe by only using words. perhaps one day i’ll provide a diagram for it. for now, words will have to do.

Summary of required design parameters #

oooooooooooookay, that was a bit long winded.

so here’s what a i need to design - a PSU board that meets the following criteria;

• must accept a 12VDC to 15VDC input power supply input
• must output an alternating waveform power delivery signal with the following attributes
  • ~43kHz frequency
  • ~-4V peak upper voltage
  • ~-11V peak lower voltage
  • must be able to deliver ~400mA of current (buffer)

now with that in mind, let’s move over to the design!